Switching regulator having terminal for feedback signal inputting and peak switching current programming

ABSTRACT

A switching regulator of a power converter is provided and includes a feedback-input circuit, a programming circuit, and a peak-current-threshold circuit. The feedback-input circuit is coupled to a terminal of the switching regulator for receiving a feedback signal. The feedback-input circuit is operated in a first range of a terminal signal. The programming circuit is coupled to the terminal for generating a programming signal. The programming signal is operated in a second range of the feedback signal. The peak-current-threshold circuit generates a threshold signal in accordance with the programming signal. The feedback signal is coupled to regulate the output of the power converter, and the threshold signal is coupled to limit a peak switching current of the power converter.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of U.S. provisionalapplication entitled “A switching regulator having a terminal forfeedback signal input and peak switching current programming”, Ser. No.61/274,297, filed Aug. 14, 2009.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is developed to minimize the pin counts of theswitching regulator or the switching controller of power converters

2. Description of the Related Art

Power converters are generally used to power many of electronic devices.The pulse-width modulation (PWM) technique is a conventional technologyused in a power converter to control and regulate the output power.Various functions, including protection functions, are built-in in theintegrated circuit of power converter to protect the power converterfrom permanent damage and for specific purpose.

To provide the additional functions to the power supply controller,additional pins are added for each function to the integrated circuitpower supply controllers. Consequently, each additional functiongenerally translates into an additional pin on the power supplycontroller chip, which results in increased costs and additionalexternal components. Another consequence of providing additionalfunctionality to power supply controllers is that there is sometimes asubstantial increase in power consumption by providing the additionalfunctionality.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of a switching regulator of a power convertercomprises a feedback-input circuit, a programming circuit, and apeak-current-threshold circuit. The feedback-input circuit is coupled toa terminal of the switching regulator for receiving a feedback signal.The feedback-input circuit which is operated in a first range of aterminal signal. The programming circuit is coupled to the terminal forgenerating a programming signal. The programming signal is operated in asecond range of the feedback signal. The peak-current-threshold circuitgenerates a threshold signal in accordance with the programming signal.The feedback signal is coupled to regulate the output of the powerconverter, and the threshold signal is coupled to limit a peak switchingcurrent of the power converter.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 shows an exemplary embodiment of a power converter;

FIG. 2 shows an exemplary embodiment of the controller in FIG. 1;

FIG. 3 shows an exemplary embodiment of the input circuit in FIG. 2;

FIG. 4 shows an exemplary embodiment of the peak-current-thresholdcircuit in FIG. 2; and

FIG. 5 shows another exemplary embodiment of the controller.

FIG. 6 shows an exemplary embodiment of the peak-current-thresholdcircuit shown in FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is best determinedby reference to the appended claims.

FIG. 1 shows an exemplary embodiment of a power converter according tothe present invention. A switching regulator 10 includes a controller100 generating a drive signal V_(W) to control a power device 20. Thecontroller 100 is powered by a supply voltage V_(DD). The power device20 is a sense MOSFET Q1 having a mirror device 25 for generating aswitching current signal V_(S) at a resistor 30. The power device 20 iscoupled to switch a transformer 15 which receives an input voltageV_(IN). The value of the switching current signal V_(S) is correlated tothe value of the switching current of the transformer 15. A rectifier 40and an output capacitor 45 are coupled to the output of the transformer15 for producing an output V_(O). A resistor 51, a shut regulator 52 (ora zener diode), and a optical coupler 50 form a feedback circuit forgenerating a feedback signal V_(FB) coupled to an input terminal FB ofthe controller 100 of the switching regulator 10. The feedback signalV_(FB) is used for regulating the output V_(O) of the power converter. Aresistor 35 is further coupled to the input terminal FB for programminga threshold signal I_(PK) which will be shown in FIG. 2 and will bedescribed in the following. The threshold signal I_(PK) is coupled tolimit the peak switching current of the power converter.

FIG. 2 shows an exemplary embodiment of the controller 100 according tothe present invention. An oscillator (OSC) 60 generates a pulse signalPLS to turn on the flip-flop 90 through an inventor 65. The flip-flop 90generates the drive signal V_(W) through an AND gate 95. The drivesignal V_(W) and the flip-flop 90 are turned off by a PWM signal S_(PWM)and an over-current signal I_(O). A comparator 71 generates the PWMsignal S_(PWM) as an output, and a comparator 72 generates theover-current signal I_(O) as an output. The outputs of the comparators71 and 72 are coupled to reset the flip-flop 90 via an AND gate 75. Aninput circuit (IN) 200 is coupled to the input terminal FB to generate alevel-shift feedback signal S_(FB), a differential signal S_(I) and anopen-loop signal S_(N). The level-shift feedback signal S_(FB) iscorrelated to the feedback signal V_(FB). The level-shift feedbacksignal S_(FB) is coupled to the comparator 71 through resistors 81 and82. The oscillator 60 further generates a ramp signal RAMP coupled to becompared with the level-shift feedback signal S_(FB) by the comparator71 for generating the PWM signal S_(PWM). The differential signal S_(I)is coupled to a peak-current-threshold circuit (I_(M)) 300, and thepeak-current-threshold circuit 300 generates the threshold signal I_(PK)according to the differential signal S_(I). The threshold signal I_(PK)is coupled to the comparator 72 to be compared with the switchingcurrent signal V_(S) for generating the over-current signal I_(O).

FIG. 3 shows an exemplary embodiment of the input circuit 200 accordingto the present invention. The input circuit 200 includes afeedback-input circuit 210 and a programming circuit. An operationalamplifier 212, a resistor 215, and transistors 211 and 220 form thefeedback-input circuit 210. The programming circuit is developed bycurrent sources 230 and 260, resistive devices 225 and 226, a resistor245, a buffer 261, operational amplifiers 241 and 242, and transistors250, 251, 252, and 253. The resistive devices 225 and 226 form adivider.

The feedback-input circuit 210 is coupled to the input terminal FB forreceiving the feedback signal V_(FB). The feedback signal V_(FB) whichis operated in a first range serves as a terminal signal. A clamp signalV_(R1) is coupled to the operational amplifier 212 to limit the maximumvalue of the first range of the terminal signal. The operationalamplifier 212 and the transistor 211 form a close loop regulator toprovide a clamped voltage (the clamp signal V_(R1)) at the outputterminal of the transistor 211. The output terminal of the transistor211 is connected to the resistor 215. The resistor 215 provides apull-high voltage for the feedback signal V_(FB) (the output of theoptical coupler 50) when the level of the feedback signal V_(FB) islower than the clamp signal V_(R1), and the transistor 211 is turned on.Once the feedback signal V_(FB) is higher than the clamp signal V_(R1),the transistor 211 will be turned off, and the signal path of theresistor 215 will be switched off as well. At this time, a constantvoltage of the feedback signal V_(FB) is determined by the currentsource 230 associates with the external resistor 35. Therefore, themaximum value of the feedback signal V_(FB) is limited by the clampsignal V_(R1). The transistor 220 is controlled by the feedback signalV_(FB) and receives a voltage source V_(CC). The transistor 220generates the level-shift feedback signal S_(FB).

The programming circuit is also coupled to the input terminal FB forreceiving the feedback signal V_(FB) and generating a programmingsignal. The programming signal is the feedback signal V_(FB) which isoperated in a second range. In other words, the feedback signal V_(FB)which is operated in the second range serves as the programming signal.The first range of the terminal signal and the second range of theprogramming signal are the voltage signals. The first range of theterminal signal is lower than the clamp signal V_(R1). The second rangeof the terminal signal is higher than the clamp signal V_(R1). Theexternal resistor 35 is coupled to determine the programming signal. Indetail, the current source 230 associates with the external resistor 35to produce the programming signal for determining the threshold signalI_(PK) (shown in FIG. 4 and FIG. 6). The programming signal is coupledto the input of the operational amplifier 241 through the dividercomposed by the resistive devices 225 and 226. A reference signal V_(R2)is connected to the operational amplifier 242. The operationalamplifiers 241 and 242, the transistor 250, and the resistor 245 form adifferential circuit to generate a current I₂₅₀ at the transistor 250.

$I_{250} = \frac{\left( {k \times V_{FB}} \right) - V_{R\; 2}}{R_{245}}$where the R₂₄₅ represents the resistance of the resistor 245, and krepresents the ratio of the divider composed by the resistive devices225 and 226.

The value of the reference signal V_(R2) is correlated to the value ofthe clamp signal V_(R1) and the ratio of divider composed by theresistive devices 225 and 226. The current I₂₅₀ is coupled to generatethe differential signal S_(I) through the current mirror transistors 251and 253.

$S_{I} = {k_{2} \times \frac{\left( {k \times V_{FB}} \right) - \left( {k_{1} \times V_{R\; 1}} \right)}{R_{245}}}$where the k₂ represents the gain (ratio) of the current mirrortransistors 251 and 253, and k₁ represents the value of (V_(R2)/V_(R1)).

Therefore, the programming signal and the clamp signal V_(R1) producethe differential signal S_(I) that is further coupled to generate thethreshold signal I_(PK). The current mirror transistors 251 and 252generate a current I₂₅₂ coupled to be compared with the current ofcurrent source 260 for generating the open-loop signal S_(N) via thebuffer 261. The buffer 261 will output the open-loop signal S_(N) oncethe current I₂₅₂ is higher than the current of the current source 260.It means the open-loop signal S_(N) is enabled when the value of theterminal signal (that is the first range) is higher than the clampsignal V_(R1).

FIG. 4 shows an exemplary embodiment of the peak-current-thresholdcircuit 300 according to the present invention. Thepeak-current-threshold circuit 300 is used for generating the thresholdsignal I_(PK) in accordance with the differential signal S_(I). Thedifferential signal S_(I) is coupled to a current source 310 forgenerating a differential current which is coupled to current mirrortransistors 311 and 312. The current mirror transistor 312 generates acurrent I₃₁₂. The current I₃₁₂ induces the threshold signal I_(PK) at aresistor 325. The maximum value of the threshold signal I_(PK) isdetermined by the current of the current source 310. The thresholdsignal I_(PK) is reduced in response to the increase of the differentialsignal S_(I).

FIG. 5 shows another exemplary embodiment of the controller 100′according to the present invention. Most circuits in the embodiment arethe same as the last embodiment shown in FIG. 2 so the description isomitted here. The main difference as the last embodiment is that thecontroller 100′ comprises a peak-current-threshold circuit (I_(M)) 400for receiving the differential signal S_(I) and the open-loop circuitS_(N) and generating the threshold signal I_(PK) according to thedifferential signal S_(I), the open-loop signal S_(N), and a pulsesignal PLS.

FIG. 6 shows an exemplary embodiment of the peak-current-thresholdcircuit 400 according to the present invention. The threshold signalI_(PK) is generated in accordance with the differential signal S_(I) andthe open-loop signal S_(N). The differential signal S_(I) produces adifferential voltage V_(I) at a resistor 350. An analog-to-digitalconverter (A/D) 360 generates a digital signal S_(D) coupled to aregister (REG) 370. The open-loop signal S_(N) is connected to a delaycircuit (DLY) 375 and an AND gate 390. The delay circuit 375 generates adelay signal S_(DLY) in response to the enable of the open-loop signalS_(N). The delay signal S_(DLY) and the pulse signal PLS are connectedto the input of the AND gate 390. The output of the AND gate 390 willgenerate a latch signal S_(L) when the open-loop signal S_(N) is enabledover a delay time. The delay time is defined by the delay circuit 375.The latch signal S_(L) is connected to clock the register 370 forsampling and holding the digital signal S_(D) into the register 370. Theoutput of the register 370 is connected to a digital-to-analog converter(D/A) 380. The output of the digital-to-analog converter 380 generatesthe threshold signal I_(PK). Thus, the latch signal S_(L) is used for asampling and holding operation performed by the register 370 of thepeak-current-threshold circuit 400 to generate the threshold signalI_(PK). In other words, the threshold signal I_(PK) is thus generatedaccording to the sampling and holding operation.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited to the disclosed embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A switching regulator of a power converter comprising: a feedback-input circuit coupled to a terminal of the switching regulator for receiving a feedback signal, wherein the feedback-input circuit is operated in a first range of a terminal signal; an external resistor coupled to the node; a programming circuit coupled to the terminal for generating a programming signal, wherein the programming signal is operated in a second range of the feedback signal, and the external resistor determines the programming signal; and a peak-current-threshold circuit generating a threshold signal in accordance with the programming signal; wherein the programming circuit comprises a current source coupled to the terminal, and the current source associates with the external resistor to produce the programming signal for determining the threshold signal, wherein the feedback signal is coupled to regulate the output of the power converter, and the threshold signal is coupled to limit a peak switching current of the power converter.
 2. The switching regulator as claimed in claim 1, in which a maximum value of the first range of the terminal signal is limited by a clamp signal.
 3. The switching regulator as claimed in claim 2, in which the programming signal and the clamp signal produce a differential signal, and the differential signal is further coupled to generate the threshold signal.
 4. The switching regulator as claimed in claim 2, in which the maximum value of the feedback signal is limited by the clamp signal.
 5. The switching regulator as claimed in claim 2, in which the programming circuit further generates an open-loop signal when the value of the terminal signal is higher than the clamp signal.
 6. The switching regulator as claimed in claim 5, in which the programming circuit further comprises a delay circuit to generate a latch signal after the open-loop signal is generated, and the latch signal is coupled to sample and hold the threshold signal.
 7. The switching regulator as claimed in claim 1, in which the first range of the terminal signal and the second range of the programming signal are voltage signals, the first range of the terminal signal is lower than the second range of the programming signal.
 8. The switching regulator as claimed in claim 1, in which the peak-current-threshold circuit performs a sampling and holding operation to generate the threshold signal. 